Title: Multilevel Algorithm for VLSI Circuit Placement


			  Nang Keung Sze
		     Mathematics Department
		    University of California
		   Los Angeles, CA 90095-1555
		   email: nksze@math.ucla.edu
	   Web page: http://www.math.ucla.edu/~nksze


Abstract: 
In this talk, a brief introduction to the VLSI circuit placement will be
given. The multilevel aglorithm/framework we used to solve the
problem will be presented. Tecniques we used in our multilevel placement
tool "mPL" (developed in UCLA VLSICAD lab) will be discussed, including
the clustering/coasening scheme, relaxation/intralevel optimization and
interpolation.