Title: Multilevel Optimization Opportunities in VLSICAD


			       Jason Cong 
                       Computer Science Department
		     Univ. of California, Los Angeles
		          Los Angeles, CA 90095
                         Email: cong@cs.ucla.edu
                     http://cadlab.cs.ucla.edu/~cong


Abstract:
The first part of the talk gives an overview of VLSI design process, in 
particular, the physical design process, including circuit partitioning, 
placement, and routing, and the associated optimization problems. Then, I 
shall present some recent results on optimality and scalability of existing 
VLSI physical design algorithms, which present significant opportunities for 
improvement.  Finally, I shall give an overview of our effort at UCLA in 
developing multilevel circuit partitioning, placement and routing tools.  In 
the subsequent talk, Prof. Tony Chan will present an in-depth discussion of 
our multilevel circuit placement tool.